1. Field of the Invention
The present invention relates to serial memories on silicon microchips, and more particularly to the production of an extended memory array by juxtaposition of a plurality of serial memories.
2. Description of the Related Art
The memories integrated into silicon chips have an integrated memory array of limited size, generally lower than the memory space required by certain applications. For example, computer peripherals such as printers require high-capacity memories to store large amounts of data. As a result, it is common practice to group together several silicon microchips to form extended memory arrays constituted by the juxtaposition of the integrated memory arrays present in each of the memories. This grouping generally involves stacking silicon microchips in a single case or stacking cases each comprising a silicon microchip.
FIGS. 1 and 2A, 2B show two classical methods enabling an extended memory array to be produced, respectively with parallel-type and serial memories.
In FIG. 1, four identical memories PMEM1, PMEM2, PMEM3, PMEM4 of parallel input/output type are grouped together to obtain an extended memory array. The memories each comprise an integrated memory array addressable under N bits (not shown). Each memory comprises N address inputs AIN−1-AI0parallel, connected to the N least significant address wires of an address bus ADB. The address bus comprises N+2 address wires, required by the addressing of the extended memory array the size of which is here four times that of the memory arrays integrated into the silicon microchips. The selection of each memory within the extended memory array is performed by means of a selecting input CS (“Chip Select”) provided on each silicon microchip. For this purpose, the two most significant wires of the address bus ADB are applied to an address decoder ADEC which supplies four selecting wires CS1, CS2, CS3, CS4, each selecting wire being connected to the input CS of a memory.
This example shows that the production of an extended memory array by means of integrated circuits with parallel inputs results in an unacceptable increase in the number of jumper wires so as to be able to individually select the memories within the extended memory array.
FIG. 2A relates more specifically to the technical field of the present invention and represents an extended memory array produced with four identical serial input/output memories SMEM1, SMEM2, SMEM3, SMEM4, or serial memories, the structure of which is schematically shown in FIG. 2B.
Each memory SMEM comprises a serial input/output IO, an input/output circuit IOCT, a central processing unit UC, an address counter ACNT of N bits and an integrated memory array MA addressable under N bits (FIG. 2B). The circuit IOCT is linked to the serial input/output IO and transforms data received in serial form into parallel data, and vice versa. Each serial input/output IO is connected to a data wire DTW (FIG. 2A) common to all the memories, which conveys commands, addresses and data in serial form at the same time. Each memory also comprises two inputs IP1, IP0 the electric potential of which is adjusted so as to allocate a determined most significant address to each memory. For example, the two inputs IP1, IP0 of the memory SMEM1 are taken to a supply voltage Vcc to allocate the most significant address “11” to the memory, the inputs IP1, IP0 of the memory SMEM2 are respectively taken to the voltage Vcc and to the ground (GND) to allocate the most significant address “10” to the memory, the inputs IP1, IP0 of the memory SMEM3 are taken to the ground and to the voltage Vcc to allocate the most significant address “01” to the memory and the inputs IP1, IP0 of the memory SMEM4 are taken to the ground to allocate the most significant address “00” to the memory.
Each memory within the extended memory array is selected by sending to the memories commands of the type [OPCODE, I1, I0, AD] comprising an operation code OPCODE, two bits I1, I0 forming a most significant address, and an address AD of N bits forming a least significant address, the most significant address forming, together with the address AD, an extended address. The central processing unit of each memory executes the operation codes OPCODE present in the commands received if the most significant address I1 I0 corresponds to the most significant address IP1 IP0 allocated to the memory. In the case of a read command, the address counter ACNT applies the N address bits AN−1-A0 present in the command to the memory array MA , while the central processing unit applies a read signal to the memory array.
U.S. Pat. Nos. 5,303,201 and 5,895,480 disclose memories of the aforementioned type, wherein the address counter (an address buffer in U.S. Pat. No. 5,895,480) is an extended address counter (or an extended address buffer) that receives an extended address instead of receiving only the least significant address. These memories work substantially in the same way as the memory described above, in that the most significant address received by the counter or the address buffer is compared to the most significant address allocated to the memory, and in that a read command is not executed if the most significant address present in an extended address is not identical to the most significant address allocated to the memory.
In summary, the usual method for obtaining an extended memory array involves providing memories capable of “self-identifying” themselves upon receiving a command comprising an extended address, and not executing the command if the most significant address included in the extended address is not identical to the most significant address allocated to the memory. This method is advantageous as far as the number of electric interconnections is concerned, but the extended memory array obtained does not have a unitary character, as far as the execution of a continuous read command is concerned, for example. Therefore, a continuous reading of the extended memory array first of all requires sending to the first memory SMEM1 a command for continuously reading its integrated memory array, such a command comprising the operation code of the command, the most significant address 1,1 of the memory SMEM1, and the least significant address AD0 designating the memory area in which the continuous reading must be initialised in the integrated memory array. Similar commands having appropriate identification bits must then be sent to the other memories, i.e., in total four commands to read the entire extended memory array.